1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a flash memory device with a multi level cell and a burst access method.
2. Description of the Related Art
A flash memory device is a nonvolatile semiconductor memory device that can electrically perform program and erase operations. In applications of a mass storage or a coded memory in a mobile device, a high capacity or high speed characteristic is increasingly required. Thus, flash memory devices are widely used. Flash memory devices can be classified into NAND flash memory and NOR flash memory. A cell array of the NOR flash memory has of memory cells arranged in parallel with respect to one bit line, while a cell array of the NAND flash memory has a plurality of memory cells arranged in series with respect to one bit line. The NOR flash memory has much higher speed in program and read operations than the NAND flash memory. Therefore, the NOR flash memory is widely used in fields that demand a high speed characteristic. The NOR flash memory, however, is very disadvantageous in terms of the degree of integration, using more chip area than other flash memory types As one of approaches to solving the limitation of the storage capacity, a multi level cell (MLC) scheme has been adopted. The MLC overcomes the limitation of a physical integration by storing multiple bits in one memory cell.
Hereinafter, terms that will be used in the detailed description of the invention will be summarized in brief.
A most significant bit (MSB) indicates data that is detected from an MLC, to which a serial sensing is applied, through a first sensing. That is, the MSB does not mean a general MSB of a digital data. A least significant bit (LSB) indicates data that is detected from an MLC, to which a serial sensing is applied, through a second sensing.
A physical address means a unit address of a cell of a memory cell, in which data is stored. A logical address is an address assigned from an outside and is not related to a memory cell arrangement.
Also, a 2-bit cell that can store 2 bits (MSB, LSB) per cell will be taken as an example. When a burst length (BL)=4/1 word=16 bits, the prior art and embodiments of the present invention will be described.
FIG. 1 illustrates a method of reading data from a 2-level cell by using a serial sensing. A parallel sensing scheme or a serial sensing scheme can be used for reading data from an MLC. The parallel sensing scheme reads a stored 2-bit data by one-time sensing, and the serial sensing scheme reads data an MSB and an LSB in sequence. A following description will be made only about a memory device using the serial sensing. Referring to FIG. 1, the serial sensing of an MLC includes a first sensing and a second sensing. The first sensing is to detect an ON/OFF-state of a cell by using a verification voltage VM so as to detect an MSB. After the MSB data is detected through the first sensing, positions of verification voltages VL1 and VL2 of the second sensing for detecting an LSB are determined by referring to the MSB data. That is, when the MSB data detected in the first sensing is “1”, a left verification voltage VL1 is selected as the verification voltage of the second sensing. On the contrary, when the detected MSB data is “0”, a right verification voltage VL2 is selected as the verification voltage of the second sensing. The 2-bit data stored in the cell is read through these successive serial sensing operations.
FIG. 2A is a block diagram illustrating a method of programming an input data read by the serial sensing in a memory device with MLCs. Referring to FIG. 2A, a plurality of external word-based data are stored in cells corresponding to physical addresses that are assigned inside in units of one word. One physical address designates MLCs for programming one complete word-based data. Specifically, when word-length data having one logical address is programmed in the cells, the data is programmed in the cells constituting one physical address. If a 16-bit length word N is inputted, all bit values of the word N are programmed in MSBs and LSBs of eight cells constituting a physical address #0. The above method is equally applied to a plurality of consecutive input words constituting one burst length. The consecutive words N+1, N+2 and N+3 followed by the word N are programmed in MSBs and LSBs of eight cells contained in a corresponding physical address. One word data having one logical address is all programmed in eight cells corresponding to one physical address.
FIG. 2B is a memory map for explaining the programmed result when the input data of one burst length are programmed in the corresponding memory cells. Referring to FIG. 2B, four 16-bit input words N, N+1, N+2 and N+3 are programmed in the corresponding eight MLCs constituting the physical addresses #0, #1, #2 and #3 of the memory cells. One input word is programmed in the cells constituting one physical address. Accordingly, one input word is stored in the bits of the cells of one physical address.
FIG. 3 is a block diagram of a configuration for reading data programmed by the method of FIG. 2. Referring to FIG. 3, sense amplifiers 10 sense data of a designated burst length from cells. A latch circuit 20 latches logic values sensed by the sense amplifier 10 in response to an MSB latch enable signal MLEN and an LSB latch enable signal LLEN, and outputs the latched data in response to a data dump signal D_Dump. An I/O buffer 30 outputs the word-based data, which are outputted from the latch circuit 20, to the outside in synchronization with a clock.
The number of the sense amplifiers 10 is equal to the number of cells storing one burst-length of data with the bits in the cell serially sensed. Thus, to detect all bit values of one designated burst length (for example, 64 bits for BL=4/16 bits=1 word) requires two sensing operations, that is, a first sensing for detecting an MSB and a second sensing for detecting an LSB.
The latch circuit 20 stores the detected data outputted through the serial sensing of the sense amplifier 10. Specifically, MSB bits of the respective cells, which are detected through the first sensing, are stored in the MSB latches allocated in each cell in response to the MLEN signal. Thereafter, when the LSB data of the respective cells are detected by the sense amplifier 10 through the second sensing, the detected LSB data are stored in the LSB latches allocated in each cell in response to the LLEN signal. Through these procedures, data corresponding to one burst length are stored in all latches of the latch circuit 20. Then, the outputs of the respective latches are activated in response to the D_Dump signal and are outputted in units of a word (I/O unit). In FIG. 3, all data of the latches corresponding to the sense amplifiers SA0 to SA7 are outputted in response to a first clock, and all data of the latches corresponding to the sense amplifiers SA8 to SA15 are outputted in response to a second clock. All data of the latches corresponding to the sense amplifiers SA16 to SA23 are outputted in response to a third clock, and all data of the latches corresponding to the sense amplifiers SA24 to SA31 are outputted in response to a fourth clock. In terms of the I/O data of the I/O buffer, bits stored in the MSB and bits stored in the LSB constitute an odd I/O and an even I/O, respectively. The D_Dump signal activates the outputs of the above-described latches, such that all latched bits corresponding to one burst length are sequentially outputted in units of words. The D_Dump signal is outputted from an internal counter and is combined in the word equal to the logical address when the outputs of the latches activated in each clock are inputted.
The I/O buffer 30 outputs the word-based output data of the latch circuit 20 in synchronization with the clock. The word stored in one physical address constitutes one I/O.
It can be seen that the conventional burst reading has to be outputted after the MSB and LSB data are all latched from the memory cell array.
FIG. 4 is a timing diagram for explaining the burst reading operation performed by the data programming method of FIG. 2 and the read path of FIG. 3. The conventional burst reading operation of the MLC memory will be described below with reference to FIG. 4.
Referring to FIG. 4, when an address detection signal nAVD indicating that the input address is valid is inputted, the MSB data of the cells are detected by the sense amplifiers 10 during the first sensing period of two clocks. At the latter part of the first sensing, when the MLEN signal is inputted such that the detected MSB data can be stored in the corresponding MSB latch, the data are prefetched by the sense amplifiers and then are latched. Then, based on the MSB data, the LSB data are detected for two clocks through the second sensing. Likewise, at the latter part of the detection, all LSB data of the cells are prefetched by the sense amplifier 10 and the latch circuit 20 latches them in synchronization with the LLEN signal. For four clocks, all data bits constituting one designated burst length are latched. Thereafter, when the D_Dump signal is inputted to the latch circuit 20, the latched data are combined in units of the words N, N+1, N+2 and N+3, and then are sequentially outputted. From the data output of FIG. 4, it can be seen that all MSBs and LSBs of the respective cells are outputted in units of words only after they are latched by the first sensing and the second sensing. The reason for this is that one word unit can constitute the complete I/O and be simultaneously outputted only when the latched bits of the MSBs and LSBs are combined, and both the MSB and the LSB has to be sensed so as to constitute one I/O. In other words, although the MSB and LSB of one cell constitute data bits of the identical I/O word unit in the output operation, the data of the word unit are always outputted after the first sensing and the second sensing are completed, because the MSB and the LSB cannot be simultaneously sensed in the serial sensing.